A NAND flash memory uses high voltages which are higher than an external power supply voltage at times of write and erase. These high voltages are generated by using a charge pump circuit functioning as a boost circuit. A program voltage VPGM, which is generated at the time of write, is supplied to a selected word line. An erase voltage VERA, which is generated at the time of erase, is supplied to a well region in which a memory cell array is formed, and is applied to a back gate of a memory cell.
An output voltage of the charge pump circuit is detected by a detection circuit, and the operation of the charge pump circuit is controlled based on an output signal of the detection circuit.